1. Field of the Invention
The invention relates to the field of semiconductor memory devices employing floating gates and the processes and methods for fabricating these devices.
2. Prior Art
One class of non-volatile semiconductor memories employs floating gates, that is, gates which are completely surrounded by an insulative layer such as silicon dioxide. Typically, a polycrystalline silicon (polysilicon) layer is used to form floating gates. These gates are electrically charged, most often with electrons by transferring charge into and from the gates through a variety of mechanisms. The presence or absence of this charge represents stored, binary information. An early example of such a device is shown in U.S. Pat. No. 3,500,142.
The earliest commerical electrically programmable read-only memories (EPROMs) employing floating gates used p-channel devices which are programmed through avalanche injection. Charge is removed from these devices by exposing the array to electromagnetic radiation such as ultraviolet light (see U.S. Pat. No. 3,660,819). Later, EPROMs used n-channel devices and relied on channel injection as the mechanism for transferring charge into the floating gates (see U.S. Pat. No. 3,984,822). Many EPROMs fabricated with current technology still rely on channel injection for transferring charge into the floating gates and radiation for erasing the gates.
Another category of semiconductor floating gate memory devices are both electrically programmable and electrically erasable. Such a device is shown in U.S. Pat. No. 4,203,158. Tunneling through a thin oxide region transfers charge into and from the floating gates. In these memories, two devices are required for each memory cell. One device includes the floating gate and the other (typically an ordinary field-effect transistor) is used to isolate the floating gate device during various memory cycles.
A more recent category of floating gate memory devices uses channel injection for charging floating gates and tunneling for removing charge from the gates. Here, each memory cell comprises only a single device and the entire memory array is erased at one time, that is, individual cells or groups of cells are not separately erasable as in current EEPROMs. These memories are sometimes referred to as "flash" EPROMs or EEPROMs.
In non-volatile memories, the programming and erasing functions occur through the tunnel oxide. In a device using the tunnel injection mechanism to erase, approximately 10 through 15 volts are applied to the source while the drain regions are floating and the control gates are grounded. During erase, electrons tunnel from the floating gate to the source from the tunnel oxide.
The relative ease with which electrons can tunnel through the tunnel oxide depends on several factors including tunnel oxide thickness, tunnel oxide quality, floating gate doping, floating gate polysilicon grain size and grain orientation, among other factors.
Electrons will tunnel at lower voltages when the grains are oriented such that sharp points are present near the floating gate/tunnel oxide interface than when there are no sharp points of the grains near the floating gate/tunnel oxide interface since edges and sharp points distort the electric field by causing it to be greater in the localized region of the edges and sharp points. In polysilicon gates with large polysilicon grain size, the variations in required erase voltages from cell to cell are large as the electric field distortion is great with large grains and there are fewer such grains in the tunnel region so that the orientation of these few grains has a large impact on the erase voltage. If there is a large variation from cell to cell in an array of such devices, those floating gates which erase faster to a verified voltage at the same erase condition are know as "tail bits". The existence of the tail bits limits both yield and cycling endurance.
What is needed is a process which forms a polysilicon floating gate with small, uniform grain sizes near the floating gate/tunnel oxide interface so that the erase voltages are thereby uniform from cell to cell and chip yield and cycling endurance is thereby increased.